1. Field of the Invention
The present invention relates to a PLL (Phase Locked Loop) frequency synthesizer and a frequency synthesizing method, and more specifically to a frequency synthesizer applicable to channel switching in mobile communication systems, wherein rapid responsibility to the switching of frequencies is required.
2. Description of the Prior Art
Referring to FIG. 1, a prior art frequency synthesizer is comprised of a voltage-controlled oscillator 3 capable of outputting a desired frequency signal 2 based upon control voltage 1, a variable frequency divider which inputs a frequency division number data signal 5 generated from a control section 4, and a frequency division number data activation signal 6 and frequency-divides frequency signal 2, a reference for oscillator 9 for outputting a reference frequency signal 8, a phase comparator 16 for comparing phases of a comparison signal 13 outputted from the variable frequency divider 7 and of the reference frequency signal 8 and outputting a pulse signal 15 which is to charge and discharge the control voltage I responsibly to a phase difference between the foregoing signals such that the phase difference is coincident with each other, a charge pump circuit 17 for actually performing charging/discharging actions based upon the pulse signal 15, and a low-pass filter 19 for integrating an output 18 from the charge pump to supply the control voltage 1 to the voltage-controlled oscillator 3. With the arrangement described above, referring to FIGS. 2 and 3, channel switching is achieved upon the output frequency being switched over from f.sub.0 to f.sub.1 during a predetermined time since a time point t.sub.1, by issuing the frequency division number data 5 corresponding to f.sub.1 before the time point t.sub.1 and issuing the frequency division number data activation signal 6 at the time point.
Such prior art frequency synthesizers, however, often suffer from a difficulty that the phase comparator 16 for use in a PLL circuit becomes severely insensitive as a phase difference between the inputted reference frequency signal 8 and the comparison signal 13 is very small. More specifically, the phase comparator 16 has a slight initial phase difference when a switched frequency width is narrow and hence the sensitivity of the phase comparator 16 is severely lowered because of the slight initial phase difference. This causes delayed detection of such a phase difference and results in a delayed initial response to the frequency switching, accompanied by a severely lengthened switching time. FIGS. 2 and 3 demonstrate responses of a prior art frequency synthesizer, in comparison, in cases where the switching width is wide and is narrow respectively.